A 0.5 V 5.96-GHz PLL With Amplitude-Regulated Current-Reuse VCO

This letter proposes an ultralow-power 5.96-GHz phase-locked loop (PLL) with a current-reuse VCO under low supply voltage of 0.5 V. While the current-reuse VCO can achieve lower power consumption, it has the drawback of amplitude-imbalance of differential outputs due to its asymmetric structure. Proposed amplitude regulation technique utilizes only one capacitor at the center-tap of the inductor, which does not require additional power consumption. The proposed PLL was fabricated in a 65-nm CMOS process. It achieved phase noise of −129 dBc/Hz at 10-MHz offset. Total power consumption was 0.69 mW under 0.5 V supply voltage.