Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique

We reported a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. This paper details a design of the proposed cascaded PLL. In order to reduce power consumption of 2nd-PLL, a power-efficient latch for pre-scaler is proposed. 3rd-1st cascaded delta-sigma-modulator can reduce the number of gates. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and −244 dB FOM while consuming 12.7mW.