Stability analysis and design methodology of near-threshold 6T SRAM cells

With the current shift towards low-voltage low-power applications, static random access memory (SRAM) cells are being operated at very-low supply voltages near the threshold voltages of the transistors. This imposes severe design challenges for conventional 6T SRAM cells. This paper presents a new quantitative analysis for the read, write, and hold noise margin of SRAM cells when operated at near-threshold voltages capturing transistor short-channel effects. Using the derived equations, an optimal design methodology is introduced to yield the SRAM cell size at a certain supply voltage for best noise-margin performance. This optimal design is verified by circuit simulations for a 6T SRAM cell implemented in 65-nm CMOS technology.