Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis

The progressive scaling of semiconductor technologies has led to significant performance improvements in digital designs. However, ultra-deep sub-micron technologies have increased the vulnerability of VLSI designs to soft errors. It is crucial to analyze this vulnerability early in the design process. In this paper we propose a new technique to model, analyze and estimate the propagation of Single Event Upsets (SEUs) in combinational designs at the Register Transfer Level (RTL) using Satisfiability Modulo Theories (SMT). The propagation of SEUs through RTL bit-vector constructs is modeled as a Satisfiability problem using the SMT theory of bit-vectors. Two different analysis techniques, concrete and abstract modeling, are used in order to investigate the efficiency and accuracy of a data type reduction technique for soft error analysis. Concrete modeling uses two versions of the design, one faulty and one fault-free, in order to analyze SEU propagation. Abstract modeling uses data type reduction to evaluate the difference in performance and accuracy over the first method. Experimental results demonstrate that the loss in accuracy due to abstract modeling depends on the design behavior. For example, for some circuits, the loss in accuracy was arround 73%, while for other circuits it was as low as 0.03%. However, abstract modeling allows reducing processing time significantly and an average reduction factor of 3.88 is reported.