A low-power time-based phase-domain analog-to-digital converter

This paper presents a low-power time-based phase-domain analog-to-digital converter (Ph-ADC). The proposed circuit employs not only the binary-search IQ-assisted algorithm, but also time-domain signal processing to extract the output digital codes corresponding to the input signal phase. Moreover, Gray codes are used in the proposed circuit to simplify the hardware implementation of the converter. Based on the proposed structure, a 4-bit 1 MS/s Ph-ADC has been designed and simulated in a standard 0.18-μm CMOS technology, with a supply voltage of 1.2 V. Simulation results show that the proposed circuit presents a signal-to-noise-and-distortion ratio (sNDR) of 25.72 dB and a spurious-free dynamic range (SFDR) of 32.9 dB at the cost of 11.46 μW.