Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects

A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (R
_{th, beol}
). The intrinsic thermal resistances of 14nm FinFETs (R
_{th0, Device}
) are extracted with face-up (conventional measurement, heat flow from the channel to substrate) and face-down (flip-chip, heat flow from the channel to metal contact) configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects R
_{th0, Device}
. The face-up R
_{th0, Device}
is higher than face-down R
_{th0, Device}
. This is more significant for multi-finger FinFETs. The volume of hot spot affects the cooling time. In an inverter, the maximum temperature (T
_max
) of pFET is higher than nFET due to the low thermal conductivity of SiGe S/D. T
_max
and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature, which may lead to an underestimation of device temperature with transient AC input.