Design of low-power two-hot finite state machines operating on double-edge clock

Synchronous controllers are finite state machines (FSM) that utilize flip-flop memory elements to store states and the clock signal to synchronize their operations. In a digital system, the activity of the clock is a major source of energy dissipation. It is responsible for 15% to 45% of the total consumed energy. Reducing the activity of the clock leads to a reduction of the total energy. An interesting strategy is designing the digital system to operate on both edges of the clock (double-edge triggered - DET), therefore allowing a 50% reduction in the frequency of the clock with the same processing rate. Synchronous FSMs, when encoded in one-hot style, also present interesting properties, but with the disadvantage of increasing the number of flip-flops and leading to higher power consumption. In this paper we propose a new method for the synthesis of synchronous FSMs that are encoded in two-hot style. The synthesized synchronous FSMs operate in both edges of the clock, therefore operating at half frequency. Although operating in both edges of the clock, only conventional flip-flops, which are sensitive to a single edge of the clock signal (single-edge transition flip-flops - SET-FF), are used. Then, although the code is two-hot, state transitions occur in the one-hot style, therefore keeping all the properties of this style.