Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell

Efficient and process variation tolerant memory is the current market demand especially for Portable devices. In scaled down devices leakage current becomes comparable to the On-State current. SRAM Cell remains in stand-by mode for most of the time and accounts for maximum average power dissipation. This research work explores the existing built-in feedback and back gate biasing techniques and proposes a 7T IG-FinFET based SRAM Topology which addresses the aforementioned issues. This 7T FinFET based SRAM Topology has been used with read decoupling which shows 44% increase in Read Noise Margin when compared to conventional 6T SG-FinFET based SRAM. Further, device sizing and back gate biasing along with built-in feedback is incorporated which saves 73 % power during standby mode and is process variation tolerant.