Memory-centric approach of network processing in a modified RISC-based processing core

The persistent rapid and vast growth of Internet's population, considering number of users, servers, links, and many new applications, has led to exponential network traffic increase, stimulating the increased demand for greater capacity of the communication network. While the fiber optic links are capable to achieve multi-gigabit bandwidth, the router's network processing hardware still remains the bottleneck for communication in networks. Therefore, in this paper we investigate the applicability of a novel memory-centric approach of network processing in a modified RISC-based processing core. The proposed processing core provides direct access to memory resources, without the use of general-purpose registers (GPRs) and cache memory, and also implements memory aliasing to specific IP header fields, thus providing easier manipulation of network packet headers. The results of Ipv4/IPv6 network processing simulations verify that the proposed network processor core achieves comparable performances to the Intel's IXP RISC micro engine.