FPGA testing points optimization method based on important analysis

From the space and time dimension, the FPGA circuit is devised some levels with “computing unit + memory/register” via analyzing the characteristics of the FPGA circuit. Combined with the location importance, the connection degree among the nodes and their own soft error probability, an importance analysis model is proposed. And then the testing points are optimized based on the importance of each node using the proposed importance analysis model. The test results indicate that the method is a feasible optimization method.