Implementation of low power reconfigurable parametric equalizer with row bypassing multiplier on FPGA

For the efficient filter implementation reconfigurability and low power have always been the main concerns. This paper introduces two new low power and high speed reconfigurable parametric equalizer designs. These designs are based on the row bypassing multipliers which are implemented using carry save adder (CSA) and ripple carry adder (RCA). The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed equalizers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with erratic coefficients that are only constrained by their order and coefficient world length. These parametric equalizers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The efficacy of the proposed design method is presented with an example. The performance of both the designs is evaluated and compared in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based parametric equalizer achieves 11% speed enhancement and 18% area reduction in comparison with RCA row bypassing multiplier based parametric equalizer. While the power dissipation of the later equalizer is 5% less than the former one.