Design and characterisation of thick oxide parasitic transistor for MIMOS 0.8-/spl mu/m CMOS technology development

The concept, design and characterisation of thick oxide parasitic transistors is investigated in this paper. The outcome includes the design from concept of two classes of thick oxide parasitic transistors, which consist of four different test structures. Both classes were used to evaluate the possibility of parasitic FET occurrence. They are class 1 (poly/field oxide and metal 1/field oxide) and class 2 (metal 1/BPSG and metal 2/BPSG/USG). Class 1 designs involved the conventional isolation technology used in the development of MIMOS 0.8 /spl mu/m CMOS technology while class 2 were designed to imitate the condition of metal routing in circuit design. The results of some n- and p-channel thick oxide parasitic transistors are presented in this paper. All field threshold voltages obtained for the test structures are above 12 V. CADENCE Virtuoso Layout editor is used to generate the test structure layouts. The results of this study complement other test structures for MIMOS 0.8 /spl mu/m CMOS technology development.