Modified synchronizer for protection from metastability

The key player in the multi-clock domain system is the synchronizer. This synchronizer suffers from the effect of metastability and results in the failure of the circuit. Prevention of the synchronizer from the metastability is feasible. Metastable state occurs whenever there is a violation of setup and hold time i.e., uncontrolled and unpredictable change in data within setup and hold time window. In this paper, we proposed a new architecture of the synchronizer. It detects any transitions in data signal within metastability window. The closed loop gains of the cross-coupled inverter are controlled by the external signal. This signal will ensure the correct state of the synchronizer. The additional part of the latch comes into action when this ambiguity occurs. The correctness of the circuit functionality is verified using HSPICE and Tanner EDA at the 32nm technology.