ASIC implementation of error detection and correction using high performance majority logic decoder

Memory is an integral and important component in most of the digital circuits. It is basically used for storing and retrieving data in many electronic circuits. In recent days, the soft errors affecting digital circuits have become the biggest challenge for memory applications. As technology is scaling down, the effect of single error upsets (SEUs) on memories further increased the concern on their reliability. Therefore this paper attempts to put forth a majority logic decoder based error detection and correction methodology. Cyclic codes are the best candidates for memory applications because of their capacity to handle large number of errors. However, the conventional technique requires large number of decoding cycles which affects the memory performance. Therefore, in this paper an attempt is made to explore an efficient error detection technique that significantly increases the speed of accessing memory whenever data read is error free. Additionally it is ensured to keep area and power consumption of the technique at optimum level. Also, the results are verified in Cadence Encounter RTL compiler 13.10 tool using 180nm technology.