2D symmetric 6T SRAM with reset

SRAM have become vital part of many VLSI chips. This in particular is true for many microprocessors, where the on chip memory size is growing with every generation to reduce the constant variance in speeds of processor and main memory. Due to improved integration, operating speeds and power dissipation have become important factors to consider in designing. In process of reducing power and delay change of topologies and scaling w/l ratio were instrumental. In this paper for the traditional 6TSRAM circuit, extra transistors are added for reset operation. In the proposed 2D SRAM with reset, to decrease the delay of the circuit biasing is done for both PMOS and NMOS using Gate Level Body Biasing (GLBB). The proposed system is designed using gpdk180 in Cadence. The functionality of the design verified using Cadence Spectre tool. The circuit has average power of 489uW with delay of 20.14ns (for d_in to d_out), 20.14ns (for write to d_out) and 44.55ps (for read to d_out). After body biasing the average power is 83.43mW (increased by 82.941mW) and delay is 20.13ns (for din to d_out: decreased by 10ps), 20.13ns (for write to d_out: decreased by 10ps) and 27.26ps (for d_in to d_out: decreased by 17.29ps). By applying the biasing the speed is increased at the cost of power. For reducing the power the transistors are sized 800nm for PMOS and 400nm for NMOS. The power was observed to be decreased to 27.22uW.