A quality characteristics estimation methodology for the hierarchy of RTL compilers

For System-on-Chips (SoCs) one of the most critical design constraints are gate count and power consumption. This paper presents a quality characteristics estimation methodology for STAR Memory System (SMS) network. Our proposed methodology is based on linear and polynomial approximation. The obtained approximate functions are embedded in scripts that were developed for automated estimation of gate count and power consumption. The mentioned methodology enables to perform area and power-aware SMS network design at early stages of SoC design.