Low-power analogue receiver ASIC for space telecommand applications

An ASIC implementation of analogue receiver focused on telecommand applications for Category A missions (Return-to-Earth, lunar and even Lagrangian missions) is presented. In addition to embedded Low-Density Parity Check (LDPC) 128 bit analogue decoder, the ASIC integrates IF coherent demodulation, carrier tracking, clock recovery, SP-L to NRZ codify data conversion and telecommand-communication unit fields recognition. Start Frame pattern analogue recognition and 2-banks analogue memory for input codeword storing are embedded too. Operation with both decoder insertion and decoder in not-correcting mode is supported. The ASIC is manufactured in XFAB 0.18um technology and assembled in PGA100 package: the die size is 5326 × 3465 um
²
. The chip features almost constant parametric performances during continuous reception and decoding from a minimum dynamic power consumption of 151mW up to a maximum of 518mW, settable by external adjustable resistance. During no-reception static operation, power consumption can be decreased by selective stand-by commands on power-demanding blocks down to 82.5mW.