Low power synthesis of sum-of-product computation in DSP algorithms

Novel techniques for low-power synthesis of sum-of-product computation are presented. The proposed synthesis techniques aim at reducing the switching activity at the inputs of the functional units leading to reduction of the internal activity as well. Heuristics are used to assign the partial products of the computation to the functional units. These heuristics increase the correlation of the partial products that will be assigned to the same functional unit thus reducing the switching activity. Next, scheduling techniques are used, to reduce the switching activity at the inputs of the functional units required for the successive evaluation of the partial products assigned to the same functional unit. Both the assignment and scheduling steps use information from both data (dynamic) and coefficients (static). Experimental results from the application of the proposed techniques on signal processing algorithms have proven that significant switching activity savings can be achieved.