A prototype router circuit for extended 2D mesh network on chips

Dependable Network-on-Chips (NoCs) are crucial for the design of recent large scale embedded systems in high-end consumer electronics products. A new NoC architecture named extended 2D mesh NoC (E2DM-NoC) has been proposed in the previous study. The E2DM-NoC is shown to be effective in the reduction of routing rules and communication latency; however, its implementation and performance have not fully studied yet. In this paper, we present a prototype router circuit to build an E2DM-NoC and design it with a hardware description language. The hardware overhead of the E2DM-NoC is also discussed.