Thin profile flip chip package-on-package development

As the demands of higher performance, higher bandwidth, and lower power consumption as well as multiple functions increases, the industry is driving advance technology developments in emerging markets, especially in portable and mobile devices to meet these requirements. The utilization of emerging technologies is pushing smaller form factor package designs with finer line width and spacing as well as improved electric and thermal performance and passive embedded technology capabilities. Due to the fast growth in emerging markets for mobile applications, a numbers of wireless devices have jumped to 4G Long Term Evolution (LTE) communication platform and may ramp to 5G generation technology in the next two to three years. In addition, advanced silicon (Si) node (20/16/14nm and below) technology development in mobile applications can pursue the die size reduction, efficiency enhancement and lower power consumption. Based on these demands and evolution of the mobile communication platform, package types become more complicated and have migrated from wirebond packaging to flip chip chip scale package (fcCSP) when higher input/output (I/O) counts are needed. For the purpose of having the shortest interconnection between logic devices and mobile low power double data rate (LPDDR) memory, three-dimensional (3D) package-on-package solutions with flip chip interconnect (fcPoP) has been widely utilized. With the ability to stack a logic processor and memory device in a single package, the utilization of fcPoP is becoming a preferred solution for achieving the best performance and efficiency as well as smaller form factor in the mobile market segment. Since the industry adopted fcPoP as a dominant package approach to address the mid to high-end mobile market, various fcPoP developments have been widely discussed. Among these fcPoP structures, bare die package-on-package (BD-PoP) and molded laser package-on-package (MLP-PoP) are the most common fcPoP types being utilized in mobile applications today. Challenges in finer pitch memory devices, thinner package profiles, stringent package warpage/coplanarity requirements as well as Surface Mount Technology (SMT) processes are being addressed. This paper reports the BD-PoP and MLP-PoP developments with a 15×15mm package size that achieve the thin profile and warpage/coplanarity targets. Through the result, low profile (total package height less than 1.2mm) solutions for both BD-PoP and MLP-PoP in mobile applications have been fabricated and demonstrated. The warpage/coplanarity control as well as reliability characterization will also illustrated, which shows these architectures are cost-effective 3D packaging solutions for highly integrated, miniaturized and low profile enabling technology.