Electrical safe operating area of low-voltage silicon carbide NMOS transistors

The trend for wide bandgap high-density power modules is the monolithic integration of low voltage wide bandgap driver circuits with high voltage power devices into a single package to reduce the parasitic from interconnects and increase the power density. With both high voltage and low voltage components in the same package, the protections of integrated circuits and system becomes very challenging. To provide sufficient protections for wide bandgap power module, the electrical safe operating area (SOA) of wide bandgap devices under reliability stress need to be understood. In this paper, the SOAs of the low voltage silicon carbide (SiC) NMOS transistors are first reported. Low voltage (i.e., 15 V) SiC NMOS transistors were fabricated using the high-temperature silicon carbide (HiTSiC) process from Raytheon Systems Limited [1]. The channel length (L) of the devices varies from 0.8 μm to 2 μm. The width (W) of the device changes from 4 μm to 20 μm. The transmission line pulse (TLP) system was used to characterize the devices under short stress pulse (i.e., 100 ns) conditions. The effects of the channel length on the SOA and the current scalability of the SiC NMOS transistors under different gate biases are demonstrated. It is observed that the typical SiC NMOS devices have a failure current (It2) of 0.2 mA/μm for L=1μm without gate bias. The electrostatic discharge (ESD) robustness of the SiC NMOS transistors is also described.