High PSRR low drop-out regulator with isolated replica feedback ripple cancellation technique

This paper presents a CMOS low-dropout regulator (LDO) with a unique power supply rejection (PSR) boosting technique. A replica device is used to cancel the power supply noise at the output that is coupled through the main LDO parasitic. The proposed LDO employs a mid-ranged output decoupling capacitor of 50nF and a comparatively low-complexity circuitry to achieve the supply rejection target while maintaining fast load transients. The proposed LDO is designed and simulated in 0.18μm CMOS process; it features a -42.1 dB PSRR at 1 MHz and about -51.06 dB at 10 MHz while driving a maximum load of 50 mA. The LDO consumes a quiescent current of 62 μA with load regulation of 0.0154 mA/mV.