A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs

This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 2
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-1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture.