Development of a reusable E1 transceiver suitable for rapid prototyping

Presents the design and development of an E1 transceiver with specifications posed by the ITU G.703 and ITU G.823 recommendations and INTRACOM S.A. (Hellenic Telecommunications and Electronics Industry, R&D Department). The development procedure is based on the use of a standard HDL and fulfils the requirements placed by industry for code reusability. The core design was successfully implemented in FPGA and ASIC technology. The verification in FPGA technology enables the rapid prototyping of a system using the specific core.