An 11b 40MS/s charge pump and comparator based pipelined ADC with variable reset voltages

This paper presents a power-efficient pipelined analog-to-digital converter targeted for applications in 4G-LTE mobile terminals. A charge pump and comparator based circuit realizes the proposed residue voltage amplification with variable reset voltages to save power. The performance of the amplification technique has been verified through simulations using a standard 0.18-μm CMOS process. It achieves 62.9-dB SNDR at 40MS/s sampling rate and consumes 5.8-mW power under a 1.8-V supply, resulting in an ENOB of 10.2-bit and an FoM of 1.2 pj/conv.-step.