Programmable gate array implementation of nonlinear co-channel interference canceller for TDMA transmission

This paper reports the performance results of an experimental study of a nonlinear co-channel interference cancellation technique for TDMA transmission. In this technique, both the desired signal and co-channel interference are estimated by nonlinear processing. An implementation of this technique by using field programmable gate array (FPGA) is described. In this implementation, a 250 k-gate FPGA chip is used in order to realize the highly complex signal processing including TCM decoding, equalization, delay profile estimation and co-channel interference cancelling. This trellis-coded co-channel interference canceller (TCC) requires 13 clocks to process one symbol, and hence it can achieve about 615 kbps processing speed at 8 MHz clock rate.