Error and flow control in terabit intelligent optical backplanes

The design of a free-space optical backplane which supports error and flow control functions is described. Traditionally, these functions are implemented in custom high-speed electronic application specific integrated circuits, which are physically removed from the optical interconnect layer. In this paper, we consider migrating these functions directly into the optoelectronic layer, yielding an "intelligent optical backplane." Conventional error control protocols are infeasible with optical backplanes since they require excessive amounts of hardware. The design of an efficient error control protocol based upon a multidimensional parity check, along with the effective flow control protocol is proposed and analyzed. The key blocks of the protocol have been implemented in 0.8- and 0.5-/spl mu/m CMOS/SEED devices and are summarized. The protocols require significantly less hardware than alternative schemes, and smart pixel arrays supporting these protocols are scalable to higher bandwidths and lower latencies. A very large scale integration analysis indicates that using 2004 technology, a free-space backplane can potentially be clocked at 1 GHz and support 24 Tb/s of bandwidth. Finally, the proposed error control protocols should be useful in optical disks and holographic memory systems, which also perform error control on large two-dimensional arrays of optical bits.