Design issues for core-based optoelectronic chips: a case study of the WARRP network router

We review trends in interconnect bandwidth requirements for multiprocessor systems and technologies proposed to meet these requirements. The benefits and costs of core-based optoelectronic chips are discussed using CMOS-SEED implementations of the WARRP network router as a case study. Results indicate that transistor density and on-chip clock rates of optoelectronic core-based designs can be reduced by as much as 40% and 30%, respectively, but aggregate off-chip bandwidth can be increased by as much as an order of magnitude as compared to all-electronic chip designs.