Design of arithmetic building blocks for cryptographic systems

The Advanced Encryption Standard (AES) is the current world standard symmetric key block cipher cryptosystem for data encryption/decryption. Multi-valued logic (MVL) is a propositional calculus that goes beyond binary in terms of the number of truth values. There has been intensive research work conducted attempting to enhance the performance of cryptographic systems in terms of speed and area. We have previously presented the gate-level logic design of a number of Modulo-4 and Galois field (GF) arithmetic operations using both binary and MVL. In this paper, we follow up on our previous work by presenting the CMOS (Complementary Metal Oxide Semiconductor) design, implementation, and PSpice simulation of Modulo-4 and Galois field (GF) arithmetic operations using MVL. The design objective is to minimize the chip area (measured by the number of transistors in the CMOS circuit implementation). Also reported is the transient analysis using the 0.18μm CMOS technology parameters. A comparison is conducted between our proposed CMOS implementation and those reported in the literature. The chip area (measured in terms of number of transistors) required for our implementation is less than those needed by the existing implementations.