Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs

In sub 1 V CMOS designs, especially around 0.5 V CMOS designs, the on-state drain current of MOSFET's shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Together with the low threshold voltage less than 0.2 V in the low-voltage CMOS, a possibility of temperature instability increases. The paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFET's and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V.