Circuit design, transistor sizing and wire layout of FPGA interconnect

This paper examines the electrical design of FPGA interconnect circuitry. We explore the circuit design of pass transistor and tri-state buffer routing switches, determine which transistor sizing, metal width and metal spacing are best for FPGA interconnect, and show that FPGA interconnect should be electrically heterogeneous-some (/spl sim/20%) of the routing tracks should be designed for maximum speed while the remainder should be more area-efficient.