An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-/spl mu/m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f/sub clock/; and 3) the function of nonreturn-to-zero clock recovery has a maximum f/sub clock//4 recovering capability with a locking range of (/spl tau//sub input//spl plusmn//spl tau//sub input//2)) where /spl tau//sub input/ is the input period.