Comparison of topside contact layouts for power dies embedded in PCB

Embedding of power semiconductor dies in PCB is a very attractive technology, especially to achieve interconnects with a very low parasitic inductance and resistance. In this paper, we focus on the contact resistance and current distribution in a large (6×6mm
²
) diode embedded in PCB, as a function of the layout of its topside contact. We demonstrate that by choosing a suitable contact layout, it is possible to achieve a very low contact resistance.