Identification of key factors to reduce stress induced during 3D IC's assembly

In this work a calibrated 3D finite element model (FEM) was used to broaden the understanding of mechanical stress induced by chip package interaction (CPI). This was done by varying geometric design parameter, such as μbump pitch, μbump array size, space between μbumps array and die thickness, and investigate their effect on mechanical stress build up during the stacking processing of 2 IC's dies. This work also includes an analyze of the use of a soft material integrated between the stacked dies to act as stress buffer and consequently reduce CPI induced stress. Looking for an alternative to optimize packaging process, thermo compression bonding (TCB) where the die is pre-heated before to be assemble to a laminate has also been investigated. The results showed that the most critical design parameter for stress, between those studied in this work, is the interconnect μbumps pitch. The results also showed a significant reduction in mechanical stress in the Si die when a buffer layer is used between the stacked dies. Last but not least, pre-heating a Si die before attaches to laminate substrate reduces the thermal strain of the laminate consequently reduces stress induced by packaging.