Effect of symmetrical underlap length on device performance of a GaN-based double gate MOSFET

GaN-based double gate DG-MOSFETs have been designed and simulated in nano-scale regime for future logic-switching applications. To minimize the short-channel effects (SCEs), both gate-to-source (G-S) and gate-to-drain (G-D) lengths, symmetrical underlap length, L
UN
, have been extended. The underlap architectured-devices exhibit better performance due to reduction of coupling capacitance between the contacts (S-G and G-D). The value of subthreshold slope (SS) and drain induced barrier lowering (DIBL) are 62.897 mV/decade and 33.59 mV/V, respectively for an underlap length, L
UN
= 8 nm with a gate length, L
G
= 12 nm.