Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application

This paper investigates the low power characteristics of transistor-based adiabatic ECRL logic styles in Sub-threshold regime for the first time in literature. Instead of the multiphase clocking, single clock source is used to enjoy the minimal power overheads. 4-2 Compressor has been implemented to validate the workability of the proposed logic in the sub-threshold regime. A vivid analysis of an 8×8 tree multiplier based on the above mentioned logic also has been implemented. The tree multiplier comprises three sub-circuits: a partial product generator, a partial product compression tree and finally a 16-bit carry look ahead adder. A uniform test bench is set up for fair comparison between the conventional CMOS based tree multiplier and ECRL based tree multiplier circuits to assure the advantage of the proposed logic in terms of power dissipation. Extensive CADENCE simulations have been done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the proposed logic circuit design in sub-threshold regime.