Design of low-power explicit type pulse-trigger generator for flip-flops

Digital designs makes use of Flip-flops (FFs) as the basic storage element. Pulse-triggered FF (P-FF), which is more popular than the master-slave based FF in high-speed applications consists of a single latch structure, hence Explicit type pulse trigger generator with pulse width control with performance optimization in power, delay, and area, design space exploration is important, In Explicit, one pulse generator can be shared by a group of FFs (e.g., an n-bit register). In this paper, a new design of explicit type pulse-trigger Generator for Flip-Flops is proposed. The pulse generator is built with three CMOS inverters along with the transmission gates, the pulse width can vary by changing the number of inverters. The proposed pulse trigger generator is compared with existing NAND logic based pulse generator [1] by simulating it over a common FF[1]FIG.2, with pulse width of approximately 132ps. The proposed pulse generator uses 9 transistors which consumes the power of 8.0 μW and NAND logic based pulse generator uses 12 transistors which consumes the power of 9.15 μW. The performance analysis of both the trigger circuits in terms of power and delay is carried out in H-SPICE and COSMOSCOPE. The power dissipation for the proposed pulse trigger Generator for FF is reduced to 11.76μw with a delay of 53.81ps.