Development and implementation of digital Phase Locked Loop on Xilinx FPGA

The subject of the article is development and an implementation of a digital Phase Locked Loop on programmable logic devices from the FPGA XILINX family. The synthesized structural diagram includes 4 MHz reference crystal oscillator, frequency pre-divider, phase frequency detector, digital filter, digitally controlled oscillator and programmable frequency divider. Different types of phase frequency detectors are developed and tested as well as different solutions for digitally controlled oscillators and programmable frequency dividers. The synchronization time, the phase jitter and the overall stability are tested for each individual configuration and different frequency relations.