Numerical analysis of the gate lag phenomena in GaAs MESFET's

A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured "hole-trap-like" DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Devices with lower surface state densities are shown to have less gate lag effect.