Correlating software modelling and hardware responses for VHDL and Verilog based designs

Modern digital system designs have been predominantly software driven, using the hardware description languages. While there are many different types of the hardware description languages, the most commonly used are VHDL (very high-speed integrated circuit hardware description language) and the Verilog. Both lend themselves to the successful realizations of the digital systems. However, even the experienced designers are often confused about which one to use and their relative performance characteristics. The authors discuss the general features of both languages from a design standpoint. Also, VHDL and Verilog based coding are discussed and the design realizations and simulations of the results are presented. We present the case studies of fundamental digital units such as full adders, comparators, counters and shift registers and discuss the timing and other important aspects which can be integrated into the actual designs. Also, the authors present a working model for hardware realizations using the CPLD (complex programmable logic device) platforms of the software designs. While it is acceptable to functionally check the designs with simulations, in actual applications, there is a need for hardware realizations as well. There are instances where the program code is sequential and the simulation results are also sequential. However, with the present complexity of CPLDs, and FPGAs where some hardware elements can be synthesized in concurrence, there can be timing problems. The authors also examine such instances and provide an insight into the arbitration schemes for a reliable digital system realization.