Hot carrier effects in nMOSFETs in 0.1 /spl mu/m CMOS technology

Recent studies show that, for a given technology, as the effective channel length is scaled down towards 0.1 /spl mu/m, the worst case hot carrier stress condition for nMOSFETs switches from I/sub b,/ /sub peak/ (peak substrate current bias condition) to V/sub g/=V/sub d/. In this paper, we demonstrate that the worst case stress condition is determined by the ratio of I/sub b/|/sub Ib,/ /sub peak/ to I/sub b/|/sub Vg=Vd/. Post-metallization anneal in deuterium similarly improves hot carrier lifetime under bias at I/sub b, peak/ and V/sub g/=V/sub d/.