Optimization of reconfigurable Si NW FETs for analog high-frequency applications

Reconfigurable field effect transistors (RFETs) are attractive for analog applications exploiting their inherent switch-ability from n-type to p-type behavior. Simulation studies by means of an experimentally calibrated 3D numerical device simulator reveal that the recently proposed simplified single gate (SG) RFET architecture leads to a two times larger intrinsic transit frequency while providing the same DC device functionality and a significantly reduced wiring effort. The inferior high-frequency performance of DG RFETs can only be partially compensated by means of a significantly increased program gate voltage.