Normally-Off GaN HFET Based on Layout and Stress Engineering

A novel normally-off GaN HFET based on layout and stress engineering is proposed and verified using technology CAD (TCAD) simulations. It requires no process modification to existing GaN HFET processes, except that passivation nitride needs to be intrinsically stressed. The device essentially consists of a normally-off low voltage (LV) HFET and a normally-on high voltage (HV) HFET. The LV HFET has a positive pinchoff voltage due to negative piezoelectric charges induced by the patterned nitride. The HV HFET is responsible to sustain most of the drain bias in OFF-state. Drain-induced barrier lowering is suppressed because of the serial configuration. Through TCAD simulations, it is shown that the device is still normally-off at a drain voltage of 1000 V. Device characteristics can be optimized merely through layout and stress engineering. With suitable choice of layout and nitride stress, the electrical performance is similar to a regular normally-on HFET.