Realization of regular ternary logic functions using double-rail logic

In logic simulation, we often have to evaluate logic functions in the presence of unknown inputs. However, the naive method often produces incorrect values. In these cases, we can produce correct values by evaluating regular ternary logic functions instead of switching functions. This paper proposes a realization of regular ternary logic functions by using double-rail logic. This implementation requires O(2/sup n//n) logic cells, and O(n) time to simulate an n-variable logic function. We showed an FPGA realization that is about 100 times faster than software simulation.