A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS

A fractional-N digital PLL with injection locking and a fractional resolution higher than the native resolution given by the number of ring oscillator stages occupies 0.042 mm
²
in 40 nm CMOS technology. It features a 400-to-1200 MHz digitally-controlled ring oscillator and in injection-locked mode, it tracks temperature and voltage changes by applying Bang-Bang phase detection re-alignment to the multiple phases of the ring oscillator. The integrated jitter is 4.34 ps
_rms
at 1.08 GHz with a reference frequency of 24 MHz and a power consumption of 7.7 mW.