Winner-take-all circuit using CMOS technology

This paper presents an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 /spl mu/A. The simulation also shows that the response time is 100 ns at a 0.2 pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD4007).