FPGA-based two-processor CPU for PLC

The paper reveals a two-processor Central Processing Unit (CPU) designed for Programmable Logic Controllers (PLC). The CPU is made up of a 1-bit (bit-type) processor and a 32-bit (word-type) processor. The both processors are operated totally independently from one another and information between them is exchanged via a exchange memory module. The 1-bit processor collaborates with edge detectors whilst the 32-bit processor is dedicated for implementation of timers and counters as well as enables execution of arithmetic operations on 32-bit integers and floating point variables. The both processors have been developed as specialized structures capable of executing control routines developed in the Instruction List (IL) programming language in line with requirements of the EN 61131-3 standard. The study presents a new approach to development of the exchange memory module and edge detectors as well as implementation of timers and counters. It is the approach that combines both software and hardware solutions, which makes them more efficient in terms of time performance as compared to already known solutions. Finally the CPU was designed with use of the hardware description language and then implemented in FPGA resources. This paper discloses results of the synthesis and execution times achieved for both individual instructions and benchmarks routines running on the newly designed CPU. The accomplished results make it possible to conclude that the CPU can be considered as an alternative solution to other units available from the market whilst the capability to execute algorithms developed in strict conformity to EN 61131-3 standard is its advantage.