Self assembled monolayer applications for nano-scale CMOS

As the CMOS technology enters into the sub 10 nm node, in order to reap the benefits of scaling, different techniques, materials and processes are required Various issues of reliability, variability and power issues are a challenge with the miniaturization of devices. Integration of bottom up processes becomes essential for meeting the scaling targets with respect to the material thickness and variability requirements. In the present work, we demonstrate the use of self-assembled monolayers for addressing the reliability and functionality issues in nano-scale CMOS.