Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application

Recently, behavior of adiabatic logic circuits have been analyzed in the literature due to the high demand for low power Portable application. In this paper, behaviors of Efficient Charge Recovery Logic (ECRL) logic structure has been analyzed in the sub-threshold regime for the first time in the literature. Proposed structures are efficacious compared to the conventional logic circuits due to very low leakage and very less amount of power dissipation. Design complexity can be reduced significantly by using single clocked supply. Static logic resembled structure of the proposed logic also reduces the silicon area. Studies of power dissipation, leakage, optimum frequency, etc. have been given analytically. Extensive CADENCE simulations in 22 nm node have been given to validate the proposed structure in sub-threshold regime.