A new approach to operation improvement of differential CMOS logic by output charge path resistance reduction

In this paper a structure for Differential Static CMOS Logic (DSCL) is proposed which uses two embedded transistors in a differential circuit. This structure introduces many modifications including Delay, Power, Power-delay-product (PDP), transient output current, time constant of circuit and outputs symmetry. The undesirable factors in Differential CMOS Logic are investigated and corrected. The circuits are simulated in HSPICE with 180nm technology and a 1.8v power supply. The proposed circuit demonstrates an improvement of approximately 24 percent in PDP.